Figure 1 – Power management Application Space

Portable Power Management Market

Handheld electronics such as PDAs, GPS receivers, games, and medical devices integrate a wide variety of logic, memory, and analog functions into a small battery powered unit. Efficiently providing power to all of the mixed signal components in such devices is a challenging proposition. A given product may have a wide number of voltage domains from 1.8V up to 40V. The core system processor may be a 1.8V or 3.3V device, the USB interface is running at 5V, LED and LED back lighting may require up to 40V supplies.

Power Sequencing

Power sequencing turns on the various voltage regulators in the correct order for power on, reset, sleep-modes, and power off states. Some voltages may require soft turn on where the voltage ramps to a requested voltage at a pre-programmed rate. This power sequencing requires digital timers and analog voltage sensing to control the sequencing and to detect over-voltage and fault conditions.

Regulator Topology Options

The power regulation topology options include linear regulators, switching regulators and low drop out (LDO) regulators. Buck regulators are used to reduce a high battery voltage down to 3.3V or 1.8V to power digital and low-voltage analog circuitry. Boost regulators are used to increase the battery voltage to provide higher voltages from 6V to 40V to such features as LED-based display
back lighting where a string of 10 LEDs can require voltages from 36 to 40V. A portable system can easily require 5 to 8 different regulators and the cost of the regulators and required support circuitry along with wasted PCB space can quickly add expense to a product.

Rechargeable Battery Management

Many portable systems contain rechargeable batteries and the power management solution has the responsibility of safely and quickly recharging the battery, monitoring of the battery’s capacity, and switching power from the battery to an external supply when connected to USB or an external transformer.

Power Management Building Blocks

Integrating the multiple power regulation components into a Triad Semiconductor via configurable array (VCA) saves on board area, component cost and manufacturing cost. Triad’s high voltage VCAs have an extensive set of mixed signal IP optimized for creating integrated power management controllers. The integrated controller saves cost and enables precise control of power sequencing, reset control, sleep-mode control, and brown-out sequencing. Triad’s power management building blocks include:

Power Management +Plus Triad VCA ASIC

Consider a typical portable application containing a microprocessor, back-lit LCD, audio, and capacitive button interfaces with the unit being powered by a lithium ion battery that is rechargeable via USB or an external power connection. This type of system has the following power management needs:

• 4.2 to 3.3V Regulation
• 4.2 to 3.3V Sleep-mode LDO Regulation
• 4.2 to 1.8V Regulation
• 5V to 4.2 Lithium-ion Battery Charging
• Battery Fuel Gauge
• Brown-Out Detector
• 36V Boost Regulator for LED-based LCD back-lighting
• Coordinated Power Sequencing for the individual Regulators

All of these functions can be integrated onto a Triad VCA. Triad’s high-voltage power management optimized VCA-2 platform is ideal for this type of application. The VCA-2 contains the following resources:

Digital Resources 9,000 Logic Gates 12 64×16 SRAM (12Kbits total SRAM) 1Kx8 EEPROM Supports multiple power regions from 2.6V to 50V Analog Resources 6 High Voltage General-Purpose Analog Tiles Each Tile has 2 op-amps plus arrays of: Capacitors, Resistors, Switches, Transistors 4 General-Purpose Analog Tiles Each Tile has 2 op-amps plus arrays of: Capacitors, Resistors, Switches, Transistors 1 High Voltage Reference Tile Boost-strapping band-gap to regulate high voltage down to 3.3V to start the power sequencing of the array 6 High Voltage Power Management Tiles 1 Reference Tile containing: Band-gap, 2 op-amps, Transistor Array for supplying bias currents 2 Wideband Amplifiers 2 Low Noise Amplifiers Analog to Digital Converter

Figure 2 - VCA-2 High Voltage Platform

The VCA-2 building blocks also enable the integration of non-power management features such as:

• Touch Screen Controller
• Capacitive Touch Button Interface
• Audio I2S Receiver
• Audio Class D Amplifier
• Audio H-Bridge
• General-Purpose Analog to Digital Converter

These functions can be combined into a single cost effect solution as shown in the ASIC block diagram in Figure 3.

Figure 3 – Power Management +Plus ASIC on Triad VCA-2

Smart Sensor Market

Smart Sensor is an umbrella term used to describe the addition of local intelligence to transducer information.

In the past, hooking up a transducer required dedicated point-to-point routing. The host processor needed to contain all of the information about the transducer before working with a sensor. A smart sensor contains interfaces to the transducer, analog processing, non-volatile memory that stores ‘datasheet’ information about the sensor, digital processing, and analog/digital communication links.

The smart sensor concept has been expressed in the family of IEEE1451 standards. These standards add Transducer Electronic Data Sheet (TEDS) information to the local sensor so that it can identify itself to the sensor network and support a plug-and-play approach to sensor integration. When a smart sensor is plugged into an acquisition network, the sensor identifies itself to the network, states what types of information will be reported, the engineering units used to report the data, manufacturer’s identification information, and extended manufacturer/user data.

Developers of smart sensor solutions are looking for these plug and play benefits while keeping transducer cost low and minimize power consumption.

Manufacturers are looking for:

Plug-and-Play - smart sensors enable easy system integration
Integration - reduce size and weight to support portable applications
Power Savings - required for portable applications
Sensor > to > Information

Transducer > Analog Interface > Data Converter > DSP > Non-volatile > Digital Communications Link

Triad VCA Building Blocks for Smart Sensor Applications

IEEE1451.4 Smart Sensor Triad VCA ASIC

Utilizing the VCA-4 platform, an IEEE1451.4 compatible Smart Sensor ASIC can be realized as shown in Figure 2 below. This ASIC provides the following features:

• Multi-Channel Analog Inputs
• Programmable Gain Amplifiers - Digitally Programmable Gain
• Low-Noise Input Amplifiers
• Single-Ended and Differential Inputs
• Analog Multiplexing
• Dual 10-bit DACs useful for external biasing or bridge excitation
• 16-bit Differential Sigma-Delta Analog to Digital Converter
• Digital Decimation and FIR Filter
• Integrated Single Cycle 8051 Microprocessor
  • RAM 3.75KB
  • EEPROM 8KB
  • Debug Interface
  • UART
  • Watchdog
• 32KHz PLL capable of generating a master clock from 32KHz to 2MHz - ideal for low-power sleep modes followed by high-speed processing and back to sleep
• UART off-chip Communication Link

This example implementation of a Smart Sensor Interface on the VCA-4 array provides high precision, low power analog processing, 16-bit analog to digital conversion, and a flexible 8051 integrated microprocessor subsystem to effectively transform raw transducer signals into useful system information. The transducer may provide raw temperature samples but the system is only interested in knowing when the temperature has gone above TEMP_MAX or below TEMP_MIN. Instead of sending the raw sensor data upstream to a central processor to manage, the local smart sensor processor reads temperature data, averages the data, and compares the results to the programmable TEMP_MAX and TEMP_MIN trigger levels. When the trigger levels are exceeded, the smart sensor sends a report to a networked central processor informing the processor that a particular sensor in the network has tripped a temperature alarm.

Non-Volatile Memory Uses in a Smart Sensor ASIC

• Reprogrammable Microcontroller
• Modify the 8051 program to accept data from different sensors enabling the ASIC to serve in more applications
• Extend the functionality of the Smart Sensor in the field via a boot-loader update of the program code over the UART serial link
• Calibration Data
• Temperature Compensation of Transducer Data
• Linearize Sensor Data
• Transducer Electronic Datasheet
  • Manufacturer ID
  • Sensor Serial Number
  • Sensor Type
  • Sensor Version
  • Amplifier Gain Settings
  • Analog and Digital Signal Path Settings
  • Sensor Data Format - Express results in engineering units
  • User defined data

Bioelectric amplifiers are used in EEG, ECG, and EMG applications like those shown Figure 1. These systems are used to measure electrical signals from the brain (EEG), heart (ECG/EKG), and muscles in general (EMG). A typical system can have from 1 to 256 sensor channels. The electrodes detect small electrical signals which require large amounts of gain and filtering to extract the information in the presence large common mode noise.

Many EEG/ECG/EMG systems are implemented as ‘boxes’ containing discrete analog circuitry to amplify and filter each sensor channel. Systems can have up to 256 channels and manufacturers are looking for:

• Integration - reduce size and weight to support portable applications
• Cost Reduction - reduce overall cost per electrode channel to support systems with up to 256 channels
• Power Savings - required for portable applications

Triad has ASIC building blocks, domain expertise in bioelectric amplifier circuit design, and existing VCA platforms optimized for the bioelectric amplifier marketplace.

Triad VCA Building Blocks for Bioelectric Amplifier Applications

4-Channel Bioelectric Amplifier Triad VCA ASIC

Utilizing the VCA-4 platform a 4-channel bioelectric amplifier can be realized as shown in Figure 2 below. This ASIC provides the following features:

• 4-channel Bioelectric Sensor Data Acquisition
• Low-Noise Input Stage: 2uVp-p input referred noise
• Input Stage Gain: 30dB
• Digitally Programmable Gain Stage: -5dB to +30dB
• Each channels gain independently settable via SPI commands
• 16-bit Sigma Delta Fully Differential Analog to Digital Converter
• Digital Decimation Filter & Stream Combiner with Serial Output
• SPI Control Interface (optionally IIC or UART)
• Package: 40-lead QFN, 6mm x 6mm

Notes:

1. Sampling frequency is adjustable by changing the ASIC master clock and/or through SPI control to change the clock generator divider ratio.
2. LPF Anti-aliasing filter cutoff frequency may be changed by changing the ASIC master clock or via SPI control. Additionally, alternative filter topologies can be implemented by schematic-only circuit changes which will require only a single mask fabrication change to the ASIC.

Triad Semiconductor develops, prototypes and produces mixed-signal ASICs in production volumes from the low thousands to the millions. It uses patent-pending single-mask Via Configurable Array (VCA) technology to create ASIC arrays using pre-designed silicon-proven analog and digital functions. This approach significantly reduces the time, cost and risk associated with full custom layout, delivering fast-turn prototypes and enabling post-design changes at minimal cost. Triad’s approach significantly reduces the engineering labor and fabrication costs of high-performance ASIC designs, and can speed “time-to-prototype” by more than half a year.

Lynn Hayden, chief executive officer at Triad Semiconductor said, “Opening Triad MDG signals a new phase in Triad’s business development. Having this Canadian subsidiary extends our support base and enables Triad to bring our cost-effective, high-performance mixed-signal ASIC designs to more companies involved in medical, industrial, communications, sensor and other applications. Customers worldwide are seeing the benefits with a lower NRE and faster time to production, along with the ability to make design changes quickly and inexpensively.”

Prescott added, “We are grateful for the assistance of Montréal International, which promotes economic development in Greater Montréal, during the key stages of our set-up, and for its continued help as we expand our activities here. Montréal has been an important center of commerce for many years, known for its aerospace, electronics, telecommunications and transportation industries, and for its engineering services and R&D. It is an ideal location for Triad MDG, and we look forward to serving companies throughout Canada and beyond with the cost and time benefits of Triad’s mixed-signal ASIC designs.”

About Triad MDG
Triad MDG, a wholly owned subsidiary of Triad Semiconductor, serves internal and customer needs for mixed-signal ASIC design. It is located at 3090 Le Carrefour Blvd., Suite 304, Laval, Quebec, H7T 2J1. Please visit www.triadsemi.com or call 514-518-8172.

About Triad Semiconductor
Triad Semiconductor is a fabless ASIC company that develops, prototypes and produces mixed-signal ASICs for production volumes from the low thousands to millions. Its patent-pending Via Configurable Array (VCA) technology creates ASIC arrays with silicon-proven analog and digital functions, reducing the time, cost and risk associated with full custom layout. Triad’s via-only routing also significantly reduces engineering effort and fabrication time, resulting in fast-turn prototypes and design changes at minimal cost. Founded in 2003 and privately held, Triad is headquartered in Winston Salem, N.C. For more information, visit www.triadsemi.com.

M. Lynn Hayden, président-directeur général de Triad Semiconductor, explique : « L’ouverture de Triad MDG marque une nouvelle étape du développement de Triad. Cette filiale canadienne nous permettra d’accroître notre infrastructure de soutien et de proposer nos solutions performantes et économiques à davantage d’entreprises développant des applications médicales, industrielles, de communications, de détection, etc. Partout dans le monde, nos clients bénéficient des avantages d’une réduction des coûts récurrents d’ingénierie et d’une mise en œuvre accélérée, tout en pouvant apporter des modifications techniques rapidement. »

Montréal International a assisté Triad Semiconductor à toutes les étapes clés du projet et continuera de favoriser l’expansion de ses activités dans le Grand Montréal. Pour M. Pierre Brunet, président du conseil d’administration de Montréal International, « la décision de Triad Semiconductor d’ouvrir sa première filiale canadienne à Laval est une excellente nouvelle, illustrant les nombreux avantages offerts aux entreprises étrangères qui décident d’investir dans la région ».

M. Prescott ajoute : « Le Grand Montréal est un important centre de haute technologie, reconnu pour ses entreprises œuvrant dans les domaines de l’aérospatiale, de l’électronique, des télécommunications, des sciences de la vie et des transports, ainsi que pour ses services d’ingénierie et de recherche et développement. C’est l’endroit idéal pour Triad MDG, ce qui nous permettra de proposer aux entreprises du Canada et d’ailleurs les avantages de nos circuits intégrés à signaux mixtes en termes d’économies de temps et d’argent. »

« La région de Montréal est également reconnue pour le dynamisme de son environnement d’affaires, sa main-d’œuvre multilingue et hautement qualifiée, l’excellente réputation de ses universités, la vitalité et la créativité de ses entrepreneurs et industries culturelles, sans oublier son coût de la vie très raisonnable et sa qualité de vie unique en Amérique du Nord », conclut M. Brunet.

Pour sa part, M. Pierre Desroches, président du conseil de LAVAL TECHNOPOLE, s’est dit très heureux d’accueillir Triad Semiconductor au sein de Laval Technopole. « Triad vient ainsi enrichir la masse critique du e-PÔLE lavallois en se joignant à un réseau d’entreprises de calibre international, capables d’inventer, de produire, de commercialiser et de compétitionner partout dans le monde », a-t-il ajouté.

Triad MDG est une filiale en propriété exclusive de Triad Semiconductor. Elle est située au 3090, boulevard Le Carrefour, bureau 304, Laval (Québec).

À propos de Triad Semiconductor (www.triadsemi.com)
Triad Semiconductor effectue le développement, le prototypage et la production sans fabrication de puces ASIC à signaux mixtes pour des volumes de production allant de quelques milliers à des millions d’unités. Sa technologie Via Configurable Array (VCA) (brevet en instance) permet de créer des matrices ASIC avec des fonctions analogiques et numériques sur silicium éprouvées qui réduisent le temps, le coût et les risques liés aux configurations entièrement personnalisées. De plus, le routage réalisé uniquement par trous d’interconnexion de Triad facilite grandement les tâches d’ingénierie et accélère la fabrication, ce qui permet de développer des prototypes et d’appliquer des modifications techniques rapidement et à un coût minime. Fondée en 2003, Triad est une compagnie privée ayant son siège social à Winston Salem, en Caroline du Nord.

À propos de Montréal International (www.montrealinternational.com)
Créé en 1996, Montréal International est issu d’un partenariat privé-public. Il a pour mission de contribuer au développement économique du Montréal métropolitain et d’accroître son rayonnement international. Montréal International a comme mandats d’attirer dans la région métropolitaine les investissements étrangers, les organisations internationales et la main-d’œuvre stratégique, ainsi que de soutenir le développement de l’innovation et des grappes de haute technologie. L’organisme est financé par le secteur privé, la Communauté métropolitaine de Montréal, la Ville de Montréal ainsi que les gouvernements du Québec et du Canada.

Depuis l’an 2000, Montréal International a contribué à 379 projets d’investissements directs étrangers totalisant 5,6 milliards de dollars. Ces investissements ont permis de créer 28 186 emplois et d’en maintenir 5 459.

Contact :

Céline Clément
Montréal International
(514) 987-9390
celine.clement@montrealinternational.com

Arrow will provide technical sales and support and product logistics for Triad’s mixed-signal ASIC customers. Triad’s patent-pending approach significantly reduces engineering labor and fabrication costs for high-performance ASIC designs, and can speed “time-to-prototype” by more than half a year.

“As designs become more highly integrated, many of our customers have been asking for mixed-signal ASIC support,” said Chris Miller, director of the customer logic solutions group of Arrow’s North America Components business. “Over the last 6 months, we’ve seen a significant interest in Triad’s technology. Customers appreciate how Triad has addressed their analog integration challenge with a competitive and flexible single-mask programmable technology. Customers are seeing the benefits with a lower NRE, faster time to production, along with the ability to make design changes quickly and inexpensively.”

“Arrow is the ideal strategic design and distribution partner, with its outstanding design support and unparalleled reach to 40,000 customers throughout North America,” said Lynn Hayden, chief executive officer at Triad Semiconductor. “Our combined efforts short circuit the time, cost and risk associated with full-custom layout, letting companies in the medical, industrial, communications, sensor and other sectors achieve cost-effective, high-performance mixed-signal ASIC designs.”

About Arrow North American Components
The North American Components (NAC) business of Arrow Electronics, Inc. is a leading provider of semiconductors and passive, electromechanical and connector products, computing solutions, services and supply-chain solutions tailored to serve distinct customer segments with dedicated sales teams. Two primary, customer-focused NAC groups serve these market segments: The Arrow Electronics Components Group serves North American-based OEM and contract manufacturing customers and the Arrow/Zeus Electronics Group targets the aerospace and military markets.

Arrow Electronics, Inc. (www.arrow.com) is a global provider of products, services and solutions to industrial and commercial users of electronic components and computer products.

About Triad Semiconductor
Triad Semiconductor is a fabless ASIC company that develops, prototypes and produces mixed-signal ASICs for production volumes from the low thousands to millions. Its patent-pending Via Configurable Array (VCA) technology creates ASIC arrays with silicon-proven analog and digital functions, reducing the time, cost and risk associated with full custom layout. Triad’s via-only routing also significantly reduces engineering effort and fabrication time, resulting in fast-turn prototypes and design changes at minimal cost. Founded in 2003 and privately held, Triad is headquartered in Winston Salem, N.C. For more information, visit www.triadsemi.com.

###

Media Contacts:
John Hourigan
Director, External Communications
Arrow Electronics, Inc.
303-824-4586
jhourigan@arrow.com

Sarah Miller for Triad Semiconductor
ThinkBold Corporate Communications
231-264-8636
sarah@thinkbold.com

These drivers can be used in such applications as; High Speed Backplane Driver, Complementary Clock Drivers, Level Translator, System Interconnects, ATM Applications, SDH Applications, High-Resolution Imaging Applications, Laser Printers, Digital Copiers, Stackable hubs for data communications, Digital Video, and High Definition Television.

Both the transmitter (LVDS_TX) and receiver (LVDS_RX) drivers support data rates up to 1Gb/s (500MHz). The LVDS_TX accepts CMOS input levels and translates them into low voltage 350mV differential output signals. The LVDS_RX accepts 350mV differential input signals and translates them to CMOS output levels. When using both blocks together in an application it provides a new alternative to high power pseudo-ECL devices for high speed applications.

For more information about these drivers, please visit the Interface section of our online IP catalog.

To IP or Not to IP

Although all real engineers would like to create all of their designs from scratch, that just is not practical in today’s fast-paced ASIC development world. The need to integrate intellectual property (IP) from third-party providers is the reality.

Engineers are also realizing that convergence is real in the ASIC world. More and more ICs are requiring the integration of digital and analog functions onto the same device. Today’s applications need digital processing coupled with analog to digital converters (ADC), digital to analog converters (DAC), PLLs, op-amps, analog filters, voltage regulators, and on and on. Even seemingly digital communication links such as USB and FireWire contain sophisticated mixed-signal physical interface (PHY) circuits. On the digital side, designers must develop or integrate communication links, microcontrollers, memory interfaces, DSP processing, and local control circuitry.

To add to the integration problem, there are not many ASIC designers that are equally well versed in both analog and digital design. Instead most are either 90% analog and 10% digital or 90% digital and 10% analog. Actually, for the digital engineers, many are 99% digital and 1% analog, but that’s a different article. (If you think you are a 50/50 or even a 60/40 designer then send me an e-mail - I would like hear from you).

The complexity of these varied development requirements coupled with time-to-market pressures force companies to consider integrating IP blocks from third-party suppliers. Advances in mixed-signal via-configurable array (VCA) technology are enabling analog soft-IP integration that emulates the rapid, efficient, and cost effective IP use found in all-digital FPGAs.

Digital IP - Difficult but Doable

When companies realize that they cannot develop all of the IP needed for an ASIC in a timely and cost effective manner, the search for third-party IP begins. In theory, digital IP has always been available in the form of GDSII layout blocks representing a particular function. Such blocks have constrained, or ‘hard,’ features–including aspect ratio, power and clock routing, internal timing, power consumption–and they are tied to exactly one process at one integrated chip (IC) foundry. With all of these fixed or hard parameters, this type of IP block has often been referred to as ‘hard IP,’ where ‘hard’ meant fixed parameters as well as hard to work with.

Digital IP sharing became widespread when designers advanced up from physical design and even schematic capture to the more interchangeable design format of a hardware description language (HDL). The adoption of Verilog and VHDL HDLs coupled with synthesis electronic design automation (EDA) tools enabled designers to express designs in a format independent of foundry, ASIC vendor library, and EDA toolset. Functions described in an HDL no longer had the fixed constraints of hard IP. An HDL IP block could be modified by synthesis to optimize its aspect ratio, timing, power, and routing resources and, most importantly, the IP was no longer tied to a particular process or foundry. The relaxation of constraints that HDL-based IP required led many to describe this new IP exchange format as ’soft IP.’

The widespread use of HDLs and soft IP makes interchange of digital IP technically feasible but integrating someone else’s IP can be a significant effort. Once a company decides to use third-party IP many different factors must be evaluated and many of them, as shown in , are not technical issues. Many companies find that a considerable amount of time and cost is associated with evaluating and integrating third-party IP.

Table 1 - Factors companies consider when integrating digital IP

The FPGA Guys - Easy to use Free IP for the Masses

There’s a dirty little saying in the EDA and IP business that goes something like ‘the best customer buys EDA tools and licenses IP and then goes out of business before ever using them.’ For the most part, the third-party IP business is setup like the EDA business, where vendors want to get all of their money on the front end. The exceptions to this approach are the FPGA companies that give away a lot of quality IP. Yes, the FPGA companies must pay for the development of their IP and pass the cost along to their customers as an increase in the silicon unit-price but since these costs are spread out across a large user base, the incremental costs are negligible. And, companies don’t pay for the IP until they are actually selling products and making money themselves. The FPGA approach focuses on removing the cost and integration barriers so that users can quickly get silicon to market and then the FPGA company makes money with the customer. FPGA vendor IP comes with a significant reduction in IP integration issues. The FPGA vendor provides consistent documentation, integration support, and a uniform development flow. By making IP easy to use and eliminating large up-front charges, FPGA products have captured a significant part of the IC market that was historically dominated by ASICs.

Analog IP Stumbling Blocks

Digital IP is a necessary part of IC development. And the FPGA IP distribution model really works. So, what is the state of analog IP? Simply put, analog IP is hard to use. Analog IP comes with all of the evaluation and integration issues associated with digital IP plus a set of issues unique to analog. Analog IP is provided as hard IP in the form of GDSII layout blocks. These blocks are fixed in size, tied to a particular foundry and process, and they are often difficult to integrate. Getting rid of noise problems from nearby circuits is often a problem due to the fixed layout of the circuits within a hard IP block. Integrating high performance analog IP with high speed digital logic on the same complementary metal-oxide-semiconductor (CMOS) die is a science and an art that, for even the best design teams, requires multiple fabrications at the foundry.

Soft IP for the Analog ASIC - Impossible yet True

What if designers could use analog IP the way they use digital IP from FPGA companies? What is needed is a framework and integration method that allows developers to easily integrate mixed-signal building blocks into complete designs. Digital IP sharing and FPGA use became pervasive as designers moved up in abstraction from physical or full-custom design. Sure, higher levels of design abstraction are slightly less efficient but companies have reaped such benefits from this approach that it is difficult to find many people doing full-custom digital design these days. If mixed-signal soft IP could be provided by an ASIC company free of charge, then companies could adopt a get-to-market-quickly approach without paying large up-front licensing fees and spending effort on third-party IP evaluation.

If a configurable approach could be brought to mixed-signal development, then analog designers could more easily reuse designs and share IP. Via-configurable array (VCA) technology incorporates silicon-proven analog and digital resources on a single semiconductor die. These resources are then covered with a global routing fabric that can be completely configured and interconnected with a single fabrication mask change, as shown in Figure 1.

Figure 1 - VCA global routing fabric configured by auto placing vias to interconnect resources

Maybe some analog designers reading this are thinking “every polygon and transistor must be hand-crafted to make an elegant design.” And, for the few cases where this is true, analog designers should stay with full-custom layout. For the vast majority of designers, however, having a set of silicon-proven configurable mixed-signal building blocks plus free mixed-signal IP would result in a real productivity improvement.

The History of Analog Arrays - Size Does Matter

In the past, configurable analog arrays consisted of either “fine-grain” or “coarse-grain” approaches. The fine-grain solutions consisted of a sea-of-transistors that could only be manually interconnected by customizing the metal and via layers of the device. This approach worked for very small analog-only designs but the routing complexity associated with this method prohibited this architecture from scaling to larger designs or designs that contained any appreciable amount of digital. The manual selection of transistors and routing also severely limited IP reuse in these architectures. The course-grain approaches consisted of large analog blocks that were configured as a limited number of macro functions such as low-pass filters or data converters. The parameters on the filters and converters could be adjusted but the large blocks could not be decomposed into smaller blocks to build other circuits. The course-grain solutions offered little flexibility and could not be used if the circuit did not match the platform macro resources.

Today’s Via-configurable Analog Arrays

Today’s configurable mixed-signal solutions, Via-configurable arrays, are built from “medium-grain” resources. Instead of being a sea-of-transistors or macro-function blocks, VCAs utilize tiles containing common analog resources that can be combined into a variety of circuits. VCA analog tiles contain operational amplifiers, buffers, and bias generators. In addition to these resources each analog tile contains arrays of capacitors, resistors, switches, transistors, and local logic, as shown in Figure 2.

VCAs are built from a variety of analog tiles optimized for single-ended, fully-differential, wide-band, lower-power, or high-voltage operation. These resources are the basic building blocks for a wide range of analog circuits such as: continuous time filters, switched capacitor filters, programmable gain stages, pulse width modulators, sigma delta modulators, analog to digital converters, and digital to analog converters. VCAs also contain high performance ADC, DAC, h-bridge, and power regulator tiles. Unlike traditional full-custom hard IP or the coarse-grained configurable IP blocks, these VCA resources are fully via-configurable, allowing them to be rearranged into other analog circuits as needed by the customer’s design using automated via-only place and route software.

Figure 2 - Mapping of an analog circuit to a via-configurable array

In addition to a fully configurable set of analog resources, VCA platforms contain digital tiles that combine logic and memory resources. These VCAs are capable of supporting high performance mixed-signal IP blocks and designs. Companies adopting VCA technology gain access to the rapid prototyping and production of mixed signal designs at a fraction of the cost of traditional full-custom development, yet with unit-pricing comparable to full-custom designs.

Creating Reusable Mixed-signal IP

Before IP can be reused, it must first be created. By comparing the VCA design process to the design process for a full-custom design, it becomes easy to see why VCA-based designs are easily reusable and why ease of design reuse is the essence of any viable mixed-signal IP concept. As shown in Figure 3, the ‘front-end’ portion of the VCA and full-custom design is identical. The first step is to split the design into analog and digital section. The digital portion of the design is captured as either an HDL or schematics, simulated, and synthesized into a gate-level netlist. The digital portion of the design is almost always captured as schematics and simulated with a SPICE-compatible simulator. Here is where the major divergence begins between the VCA and full-custom design flows.

Figure 3 - VCA flow facilitates soft IP reuse compared to full-custom’s hard IP output

Full-custom Layout

In a full-custom design, schematics and simulation are only rough models to guide the engineer in the “back-end” portion of the design. In the full-custom approach, the “back-end” portion of the design involves manually creating transistors and other circuit elements out of polygons in a layout editor. The “front-end” schematic database does not drive the layout process, instead the engineer acts as the manual synthesis, placement, and routing “tool” that creates every transistor and polygon in the design. Since all of the polygons and their interactions are new, the design must undergo physical extraction to determine the parasitics and couplings between adjacent and not-so-adjacent circuit structures. This parasitic/coupling analysis loop may require several iterations and is often a source of delay and increased expense in full-custom development efforts. Once the designer completes the “back-end” of the design, the output is a rectangular block of transistors with a rigid set of parameters that will be difficult to integrate or modify for future designs.

Via-configurable Arrays Enable Mixed-signal Soft IP

VCA architectures do not require full-custom layout because the mixed-signal resources are pre-placed along with a global routing fabric. The invention of analog-aware, via-only automatic place and route software allows the manual layout “back-end” to be replaced with an automated place and route “back-end.” Just as in digital design, where the HDL or schematic drives the synthesis and place and route process, the analog schematic and netlist in a VCA flow is the last manual step required to create a design or IP block. In the VCA flow, the digital gate-level netlist is merged with the analog SPICE-level netlist and this mixed signal netlist is the input to the via-only place and route software. As shown in Table 2, by capturing design intent at the schematic/netlist level, designers can create and reuse a wide range of mixed-signal IP blocks.

Table 2 - Reusable VCA mixed-signal soft IP

Designers can understand and integrate schematics and netlists much more readily than they can hard IP blocks. By providing designers with the ability to capture design intent in a “soft” format, VCA vendors will encourage the sharing and reuse of mixed-signal IP the same way that HDLs and synthesis enabled digital-only “soft-IP” reuse. Since VCA technology utilizes a single fabrication mask and requires no full-custom layout, the development time and cost, risk, and fabrication cost are reduced to the point that VCA development appears more like designing an FPGA than like the traditional full-custom endeavor. Like the FPGA companies, VCA providers are fabless semiconductor companies interested in selling silicon. As well as enabling customers to take advantage of with low development costs, VCA companies will encourage the use of their technology by providing low-cost development coupled with an ever-expanding and free mixed-signal IP library and with unit-pricing and performance on par with full-custom designs.

There are many reasons for the early demise of the digital structured ASIC market. A leading candidate is the market itself. The severe downturn in the economy led to depression-like times in the technology segment. ASIC starts went way down. Companies were not looking to spin a new ASIC. Most were happy to let designs grow old and age gracefully. Just as this perfect storm is forming, the push for structured ASICs takes life.

Digital ASIC companies have been trying to retain market share for years. FPGA offerings have continued to advance, taking over large segments of the ASIC market. Gate array ASICs had early success as customers were looking for cost competitive ways to convert from expensive FPGAs. The big FPGA companies, not willing to let their market erode, continued to expand their product and tools. Before long, the price advantage for conversions was gone. The FPGA-to-ASIC conversion market stagnated.

While continuing to support their core technology - cell-based ASICs - companies were looking for ways to regain market share. Enter structured ASICs. All the good stuff associated with gate array ASIC products - lower NRE, lower mask costs. None of the bad stuff associates with standard cell ASICs - long design time, significant design risk, high mask cost.

Digital Structured ASICs predefine most of the layers of an IC with pre-placed logic gates and memory. The user’s design is then configured and interconnected by customizing the last few metal layers. This simplified design and manufacturing process can yield lower cost and lowered risk. Technology size goes down, NRE goes up, ASP goes down. Overall cost, NRE + ASP is lower.

Early adopters wrote many articles predicting the potential size of the structured ASIC market. As late as 2004 it was predicted that the structured ASIC market would grow to $1.4B by 2008. Other predictions talked about a $2.5B market by 2009.

The structured digital ASIC provided a way for the ASIC guys to combat the standard product guys. With the advantages of faster time to market and a lower cost barrier, the early predictions of a robust digital structured ASIC market were understandable. Wrong, but understandable.

Mixed signal structured ASICs follow a similar technology path as their digital counterparts. Simply, they process analog and digital signals on a single chip. Until now, mixed signal ASIC design has required time consuming, expensive, and risky full-custom (manual) layout.

Using a structured approach with a mixed signal ASIC allows designers to create mixed signal ASICs using a single via layer. Full-custom layout not required.

The question is whether the downfall of the digital structured ASIC market is a leading indicator for the mixed signal structured ASIC market. If the underlying factors were the same, the answer should be the same. They are not. Here’s why:

When you lower the barrier of entry, namely NRE, you open up the ASIC possibilities to a new (and large) group of customers. Being able to prototype a device in the same technology that will be used in production is much more useful to designers than kluging together discrete digital and analog functions. Reducing risk by using IP blocks that have been silicon proven allows designers to implement functions that they know will work the first time. Reducing the time to go from design - to prototype - to production - gives companies looking to implement a mixed signal ASIC a competitive advantage.

You can buy a mixed signal FPGA. There are applications where a mixed signal FPGA will support your requirements. But, the possibility of solutions on the mixed signal side is much smaller than in the digital world. In the digital space, entire categories of ASIC devices have been eliminated by using an FPGA or ASSP. These alternatives offer no NRE, no risk and low unit price. That offering is much smaller in the mixed signal space. The mixed signal designer has fewer options from which to choose. Go the full-custom mixed signal ASIC route, meet your design requirements, integrate all the custom code and features that make your end product unique. Shoe horn your requirements into a standard product or mixed signal FPGA and loose some of the cool features that enable to sell your products at a high margin.

Or - give customers an option. The best of both worlds. Via-configured arrays. Structured mixed signal ASICs. A solution that truly fills the gap for the mixed signal ASIC designer. With history as a guide, mixed signal ASIC companies looking to provide customers with a viable solution should do just fine.

Visit Triad Semiconductor, www.triadsemi.com , for more information about Triad’s revolutionary via configurable array (VCA) technology that enables the rapid creation of low cost, low risk, rapid time to market mixed signal ASICs.